In the field of data switching, the performance of data switching nodes participating in data transport networks is of outmost importance. The range of features supported and the array of deployable services is of an equally high importance.
FIG. 1 is a schematic diagram showing general functional components of a data switching node 100. The data switching node 100 is a multi-ported device having a shared memory 102 design and forwarding Protocol Data Units (PDUs) between N physical ports 104 in accordance with supported data transfer protocols. Although pictured as such, the invention is not limited to data switching equipment having a shared memory design.
PDUs include and are not limited to: cells, frames, packets, etc. Each PDU has a size. Cells have a fixed size while frames and packets may vary in size. Each PDU has associated header information used in forwarding the PDU towards a destination data network node in the associated data transport network. The header information is consulted at data switching nodes in determining the output port via which to forward the PDU towards the destination data network node. More than one output port may be determined to forward a PDU to as is the case for PDUs multicasted to a group of data network nodes.
Each physical port 104 is adapted to receive and transmit data via an associated physical link 106 as shown at 108. Each physical port 104 has an associated physical data transfer rate. Physical port 104 designs having an adjustable physical data transfer rate exist. Physical ports 104 can also be used to convey data adhering to more than one data transfer protocol. A design requirement is that the data switching node 100 be able to process and convey PDUs such that all physical ports 104 receive and transmit simultaneously at their full physical data transfer rates. The operation of each physical port 104 is controlled via associated physical port operational parameters.
The overall operation of a data switching node 100 includes: receiving at least one PDU via an input port 104, determining an appropriate output port 104 to forward the PDU to, scheduling the PDU for transmission, and transmitting the PDU via the determined output port 104. In determining the appropriate output port, PDUs may be stored in processing queues in the shared memory 102. Each physical port 104 has access to the shared memory 102 via a data bus 110. Processing queues are used to: match data transfer rates, match data transfer rates with processing rates, enable data flow rate estimation and enforcement, evaluate processing rates, enable statistics gathering, etc.
Although in principle, the operation of data switching node 100 is simple, the implementation of such data switching equipment is not trivial. Efficient operation of the data switching node 100 is dependent on an efficient management of resources and efficient deployment of services.
The header information is also consulted in: managing the operation of the data switching node 100, managing resources of the data switching node 100 and to some extent data network resources associated therewith, provisioning data services, etc.
Managing the operation of the data switching node 100 and managing resources at the data switching node 100 is essential for efficient data switching performed by a switching processor 120. In forwarding PDUs, the switching processor 120 makes use of a PDU classifier 122 to inspect PDUs pending processing and to inspect a body of routing information provided by an associated destination address resolution function 124 to determine output ports 104. The PDU classifier 122 also makes a determination whether PDUs are unicast or a multicast.
In processing PDUs, the body of routing information may be modified. Modifying the body of routing information is necessary in establishing new data transport routes in the data transport network for data sessions and the associated data transfers. As the header information is processed, the data switching node 100 learns of new data network nodes. In determining output ports 104 to forward PDUs to, the data switching node 100 learns of new routes to destination data network nodes.
The body of routing information can be stored in the shared memory 102. The sharing of data storage resources for PDU buffering and for storing routing information, consolidates the memory storage requirements at the data switching node 100 and simplifies the design of the data switching node 100 leading to reduced implementation costs.
An exemplary resource management function relates to data flow rate enforcement 130. Another resource management function and to some extent an operational management function of the data switching node 100 is provided via data flow statistics gathering 132. Link layer operation is managed through a port monitoring function 140.
An example of a service includes virtual networking supported at the data switching node 100 via a virtual networking function 150. By deploying new services, the data switching node learns of new Virtual Local Area Network (VLANs) being established, etc. PDU header information is consulted to determine PDU treatment characteristics such as VLAN associativity in support of the virtual networking function 150, Class-of-Service (CoS) associativity in providing Quality-of-Service (QoS) guarantees in support of a Service Level Agreement (SLA) enforcement function 160, PDU forwarding priorities in support of data streaming functionality, etc.
The learning ability of the data switching node is largely controlled by learning protocols which collectively provide data transport network topology discovery features. The learning ability is also limited by processing resources available at the data switching node such as processing power, memory storage resources, processing bandwidth, etc.
Manufacturers of data switching equipment have been under a high market pressure to reduce component count which led to embedded designs. Learning protocols used by the data switching nodes are typically embedded and form an integral part of the firmware/software executed during the operation of the data switching node.
FIG. 2 is a schematic diagram showing an exemplary implementation of a data switching node affecting resource management and delivering data services.
Typical embedded designs of data switching equipment make use of a microcontroller 200 to enable an unmanaged operation thereof. The microcontroller 200 is factory programmed to support a specific feature set enabling the data switching node to function autonomously.
The microcontroller 200 interfaces with the shared memory 102 to access PDU data and other data used in processing PDUs such as but not limited to the above mentioned body of routing information.
In implementing the destination address resolution function 124, the microcontroller 200 interfaces with a Media Access Control (MAC) control database 210 storing tables specifying destination data nodes identifiers reachable via each physical port 104. The port monitoring function 140 may also use the same the MAC control database 210 to store operational parameters of each physical port 104 including data transfer rates, data transfer protocols supported, parameters associated with data network topology discovery, link status, etc. In support of the port monitoring function 140 the microcontroller 200 interfaces with each physical port 104 to obtain information, monitor and change operational parameters thereof.
In implementing the data flow rate control function 130, the microcontroller interfaces with a PDU processing queue control block 220 and a rate control block 222. The PDU processing queue control block 220 tracks the usage of memory buffer space in the shared memory 102 via registers holding queue size values, queue locations in the shared memory 102, etc. The rate control block 222 stores registers specifying: queue low watermark occupancy levels, queue high watermark occupancy levels, current queue occupancy status for each processing queue, current data throughput rate for each processing queue, current data throughput status for each processing queue, data flow variables, whether flow control is enabled, etc.
In implementing the virtual networking function 150, the microcontroller 200 interfaces with a VLAN index table 230 and a VLAN spanning tree database 232. The VLAN index table 230 stores associations between data network node identifiers and virtual network identifiers, data transmission priorities for virtual network associated data, data transmission parameters including bandwidths, etc. The VLAN spanning tree database 232 stores a hierarchical association between virtual networks and related parameters.
In implementing the statistics gathering function 132, the microcontroller interfaces with a statistics counter block of registers 240 holding values for statistics counters. Examples of statistics counters include but are not limited to number of PDUs received, number of PDUs transmitted, number of bit errors instances, etc. There are global statistics counters, port statistics counters, service specific statistics counters, etc.
The presented design can be reduced to a single silicon chip. Such embedded designs although providing for a very compact data switching node tend to be proprietary, not easily upgradeable, non-scaleable, etc. The supported feature set tends to be limited by what was typically required of data switching equipment at the time of development.
For managed mode operation a management processor 250 may be used mainly for status reporting and higher level functions. The operational status of the data switching node is brought to the application layer and out to monitoring software applications such as network management applications perhaps, remote from the data switching node 100. A proprietary data connection 260 is provided between the microprocessor 200 and the management processor 250.
In operation the microcontroller 200 and management processor 250 are used together to manage resources and deliver services. Functions of the embedded microcontroller 200 include: initialize internal and external memory registers, the coordination of information synchronization between the above mentioned components including the management processor 250, send commands to components for execution, receive reports from components, alert the management processor 250 component of operation critical events detected by other components, etc.
Current designs have been implemented using a large number of memory access registers to reference different memory locations in enabling information exchange. In enabling the reporting of critical events, as many as 20 interrupt sources per physical port 104 have been used but, by provisioning access thereto via the above mentioned registers, the management processor 250 needs to reference multiple hierarchical registers to determine the interrupt source and service it.
The microcontroller 200 is programmed with specific information exchange protocols for each component to enable the implementation of each function. The development of additional functionality and the addition of new features in support of enhanced and new services, necessitates the re-coding of the microcontroller 200. Any upgrade of any of the components including the management processor 250 also requires the re-coding of the microprocessor 200.
Therefore there is a need to provide enhanced methods of monitoring the performance of data switching nodes as well as providing support for service delivery in enhancing the performance of the data switching node 100.